Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
A typical non-volatile memory device is a type of memory in which the array of memory cells is typically organized into memory blocks that can be erased and reprogrammed on block-by-block basis instead of one byte at a time. Changes in a threshold voltage of each of the memory cells, through erasing or programming of a charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The data in a cell of this type are determined by the presence or absence of the charge in the charge storage structure.
Non-volatile memory devices typically have a reserved area in the memory array for redundant columns (e.g., bit lines) of memory cells. The redundant columns can be used when a particular address is determined to indicate a defective memory cell (with such an address being sometimes referred to herein as a “defective address”). For example, a bit line-to-bit line shorting condition or a single cell failure can use a redundant column to repair the defective condition.
Mapping a redundant column to a defective column typically comprises comparing each received address to a list of defective addresses while a data load operation is being performed. If an address to be programmed is found to be defective, the system deselects the defective address and selects the corresponding redundant column. Since the comparing is performed in real time as the data to be programmed is loaded into the page buffer, the architecture needs to be fast enough to follow the I/O speed in order to reduce any data bottlenecks. This can result in difficult design constraints for timing purposes.
The redundant column mapping also maps an entire column when only a single memory in a column has been determined to be defective. For example, one defective memory address can result in a byte or more of the redundant column area of the memory array being assigned to repair the defective address. This can result in an ineffective use of redundant columns of memory cells.
For the reasons stated above and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a more efficient scheme for redundancy.